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W39V080FA data sheet 1m 8 cmos flash memory with fwh interface publication release date: dec. 13, 2005 - 1 - revision a5 table of contents- 1. general des cription ......................................................................................................... 3 2. features ....................................................................................................................... .......... 3 3. pin config urations............................................................................................................. 4 4. block diagram .................................................................................................................. .... 4 5. pin descri ption................................................................................................................ ..... 4 6. functional d escription.................................................................................................... 5 6.1 interface mode selecti on and descri ption...................................................................... 5 6.2 read (write ) mode ......................................................................................................... 5 6.3 reset oper ation.............................................................................................................. 5 6.4 accelerated program operation ..................................................................................... 5 6.5 boot block operation and hardware prot ection at initial- #tbl & #wp ........................ 5 6.6 sector eras e command ................................................................................................. 6 6.7 program oper ation ......................................................................................................... 6 6.8 dual bios ...................................................................................................................... .6 6.9 hardware data protection .............................................................................................. 6 6.10 write operati on status ................................................................................................... 7 6.10.1 dq7: #data polling.........................................................................................................7 6.10.2 ry/#by: read y/#busy ...................................................................................................7 6.10.3 dq6: toggl e bit ..............................................................................................................7 6.10.4 dq5: exceeded ti ming limi ts ........................................................................................8 6.11 identification input pin id[3:0] ......................................................................................... 8 6.12 register....................................................................................................................... .... 8 6.12.1 general purpose i nputs regi ster ...................................................................................8 6.12.2 block locking r egisters .................................................................................................8 6.12.3 product identificati on regist ers ....................................................................................10 6.13 table of operat ing modes ............................................................................................ 11 6.13.1 operating mode selecti on - programme r mode ...........................................................11 6.13.2 operating mode sele ction - fw h mode .......................................................................11 6.14 fwh cycle de finiti on ..................................................................................................... 12 6.15 embedded programmi ng algorit hm.............................................................................. 13 6.16 embedded erase al gorithm.......................................................................................... 14 6.17 embedded #data polli ng algorit hm.............................................................................. 15 6.18 embedded toggle bi t algorit hm ................................................................................... 16 6.19 software product identification and boot blo ck lockout detection acquisition flow .. 17 7. dc character istics .......................................................................................................... 18 7.1 absolute maximu m ratings .......................................................................................... 18 7.2 programmer interface mode dc o perating characteristics ......................................... 18 7.3 fwh interface mode dc oper ating characte ristic s..................................................... 19 7.4 power-up ti ming........................................................................................................... 19 7.5 capacitance .................................................................................................................. 19
W39V080FA - 2 - 8. programmer interface mode ac characteristics ............................................. 20 8.1 ac test co nditi ons ....................................................................................................... 20 8.2 ac test load and waveform ....................................................................................... 20 8.3 read cycle timi ng parame ters.................................................................................... 21 8.4 write cycle timi ng parame ters .................................................................................... 21 8.5 data polling and toggle bi t timing para meters........................................................... 21 9. timing waveforms for prog rammer interf ace mode ....................................... 22 9.1 read cycle timi ng diagram......................................................................................... 22 9.2 write cycle timi ng diagram ......................................................................................... 22 9.3 program cycle ti ming diag ram.................................................................................... 23 9.4 #data polling timi ng diagra m .................................................................................... 23 9.5 toggle bit timi ng diagram ........................................................................................... 24 9.6 sector erase ti ming diagr am....................................................................................... 24 10. fwh interface mode ac character istics ............................................................... 25 10.1 ac test co nditi ons ....................................................................................................... 25 10.2 read/write cycle ti ming parame ters .......................................................................... 25 10.3 reset timing paramete rs ............................................................................................. 25 11. timing waveforms for fwh interfac e mode.......................................................... 26 11.1 read cycle timi ng diagram......................................................................................... 26 11.2 write cycle timi ng diagram ......................................................................................... 26 11.3 program cycle ti ming diag ram.................................................................................... 27 11.4 #data polling timi ng diagra m .................................................................................... 28 11.5 toggle bit timi ng diagram ........................................................................................... 29 11.6 sector erase ti ming diagr am....................................................................................... 30 11.7 fgpi register/product id readout timing diagram.................................................... 31 11.8 reset timing diagram .................................................................................................. 31 12. ordering info rmatio n..................................................................................................... 32 13. how to read the top marking...................................................................................... 32 14. package dime nsions ......................................................................................................... 33 14.1 32l plcc ..................................................................................................................... 33 14.2 32l stsop (8 x14mm)................................................................................................. 33 14.3 40l tsop (10 mm x 20 mm)........................................................................................ 34 15. version hi story ................................................................................................................ .35
W39V080FA publication release date: dec. 13, 2005 - 3 - revision a5 1. general description the W39V080FA is an 8-megabit, 3.3-volt onl y cmos flash memory organized as 1m 8 bits. for flexible erase capability, the 8mbits of data are di vided into 16 uniform sectors of 64 kbytes. the device can be programmed and erased in-system with a standard 3.3v power supply. a 12-volt vpp is required for accelerated program. the unique cell architecture of the W39V080FA results in fast program/erase operations with extremely low curre nt consumption. this device can operate at two modes, programmer bus interface mode and fwh bus in terface mode. as in the programmer interface mode, it acts like the traditional flash but with a mu ltiplexed address inputs. but in the fwh interface mode, this device complies with the intel fwh spec ification. the device can also be programmed and erased using standard eprom programmers. 2. features ? single 3.3-volt operations: ? 3.3-volt read ? 3.3-volt erase ? 3.3-volt program ? fast program operation: ? vpp = 12v ? byte-by-byte programming: 9 s (typ.) ? fast erase operation: ? sector erase 0.9 sec. (typ.) ? fast read access time: tkq 11 ns ? endurance: 30k cycles (typ.) ? twenty-year data retention ? 16 even sectors with 64k bytes ? any individual sector can be erased ? dual bios function ? full-chip partition with 8m-bit or dual-block partition with 4m-bit ? hardware protection: ? #tbl supports 64-kbyte boot block hardware protection ? #wp supports the whole chip except boot block hardware protection ? hardware features ? ready/#busy output (ry/#by) ? detect program or erase cycle completion ? hardware reset pin (#reset) ? reset the internal state machine to the read mode ? vpp input pin ? acceleration (acc) function accelerates program timing ? low power consumption ? read active current: 15 ma (typ. for fwh mode) ? automatic program and erase timing with internal v pp generation ? end of program or erase detection ? toggle bit ? data polling ? latched address and data ? ttl compatible i/o ? available packages: 32l plcc, 32l stsop, 40l tsop(10 x 20 mm), 32l plcc lead free, 32l stsop lead free and 40l tsop (10 x 20 mm) lead free
W39V080FA - 4 - 3. pin configurations #we(fwh4) dq4(rsv) dq3(fwh3) dq7(u/#l) dq6(d/#f) #oe(#init) dq5(rsv) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 32l stsop 24 23 22 21 20 19 18 17 a3(id3) ic r/#c(clk) nc v dd a10(fgpi4) vpp a9(fgpi3) a8(fgpi2) #reset a7(fgpi1) a6(fgpi0) a2(id2) a1(id1) a0(id0) dq2(fwh2) dq1(fwh1) dq0(fwh0) a5(#wp) a4(#tbl) v ss v ss ry/#by(rsv) nc nc #we(fwh4) dq3(fwh3) dq2(fwh2) dq1(fwh1) dq0(fwh0) 1 40l tsop 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vpp vdd clk a9(fgpi3) a8(fgpi2) nc vss vss vdd dq7(u/#l) dq6(d/#f) vdd vss nc ic a4(#tbl) a5(#wp) 2 3 4 5 6 7 24 21 22 23 nc nc nc a10(fgpi4) nc #reset nc nc a7(fgpi1) a6(fgpi0) dq5(rsv) dq4(rsv) a0(id0) a1(id1) a2(id2) a3(id3) #oe(#init) 9 10 11 12 13 14 15 16 8 17 18 19 20 ry/#by(rsv) a 1 0 ^ f g p i 4 v 5 6 7 9 10 11 12 13 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 ^ f w h 1 v v s s d q 6 ^ d / # v # r e s e t v d d r / # c ^ c l k v a 9 ^ f g p i 3 v 32l plcc dq0(fwh0) a7(fgpi1) a6(fgpi0) a4(#tbl) a3(id3) a2(id2) a1(id1) a0(id0) a5(#wp) ic dq7(u/#l) #we(fwh4) #oe(#init) nc a 8 ^ f g p i 2 v d q 2 ^ f w h 2 v d q 3 ^ f w h 3 v d q 4 ^ r s v v d q 5 ^ r s v v v ss v dd nc v p p ry/#by(rsv) f 4. block diagram program- mer interface 0fffff 000000 020000 01ffff 010000 00ffff #reset ic a[10:0] dq[7:0] #oe #we r/#c fwh interface clk fwh4 fwh[3:0] 0f0000 0effff 64k bytes block 0 030000 02ffff #init #wp #tbl 0e0000 0dffff 0d0000 0cffff 64k bytes block 1 64k bytes block 2 64k bytes block 13 64k bytes block 14 64k bytes block 15 ry/#by 5. pin description interface sym. pgm fwh pin name ic * * interface mode selection #reset * * reset #init * initialize #tbl * top boot block lock #wp * write protect clk * clk input fgpi[4:0] * general purpose inputs id[3:0] * identification inputs pull down with internal resistors fwh[3:0] * address/data inputs fwh4 * fwh cycle initial d/#f * dual bios/full chip pull down with internal resistors u/#l * upper 4m/lower 4m pull down with internal resistors r/#c * row/column select a[10:0] * address inputs dq[7:0] * data inputs/outputs #oe * output enable #we * write enable ry/#by * ready/ busy vdd * * power supply vss * * ground vpp * * accelerate program power supply rsv * * reserved pins nc * * no connection
W39V080FA publication release date: dec. 13, 2005 - 5 - revision a5 6. functional description 6.1 interface mode selection and description this device can operate in two interface modes, one is programmer interface mode, and the other is fwh interface mode. the ic pin of the device pr ovides the control between these two interface modes. these interface modes need to be configured before power up or return from #reset. when ic pin is set to high state, the device will be in the programmer mode; while the ic pin is set to low state (or leaved no connection), it will be in the fwh mo de. in programmer mode, this device just behaves like traditional flash parts with 8 data lines. but t he row and column address inputs are multiplexed. the row address are mapped to the higher internal address a[19:11]. and the column address are mapped to the lower internal address a[10:0]. for fwh mode, it complies with the fwh interface specification. through the fwh[3:0] and fwh4 to comm unicate with the system chipset . 6.2 read (write) mode in programmer interface mode, the read (write) op eration of the W39V080FA is controlled by #oe (#we). the #oe (#we) is held low for the host to obt ain (write) data from (to) the outputs (inputs). #oe is the output control and is used to gate dat a from the output pins. the data bus is in high impedance state when #oe is high. as for in the fw h interface mode, the read or write is determined by the "bit 0 & bit 1 of start cycle ". refer to the fwh cycle definition and timing waveforms for further details. 6.3 reset operation the #reset input pin can be used in some applicati on. when #reset pin is at high state, the device is in normal operation mode. when #reset pi n is at low state, it will halt the device and all outputs will be at high imp edance state. as the hi gh state re-asserted to the #reset pin, the device will return to read or standby mode, it depends on the control signals. 6.4 accelerated pr ogram operation the device provides accelerated program operations through the acc function. this function is primarily intended to allow a faster manu facturing throughput in the factory. 6.5 boot block operation and hardware protection at initial- #tbl & #wp there is a hardware method to protect the top b oot block and other sectors. before power on programmer, tie the #tbl pin to low state and then the top boot block will not be programmed/erased. if #wp pin is tied to low state before power on, the other sectors will no t be programmed/erased. in order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (s ee command codes for identification/boot block lockout detection for specific code), and then r ead from address ffff2(hex). you can check the dq2/dq3 at the address ffff2 to see whether the #tbl/#wp pin is in low or high state. if the dq2 is ?0?, it means the #tbl pin is tied to high state. in such condition, whether boot block can be programmed/erased or not w ill depend on software setting. on the ot her hand, if the dq2 is ?1?, it means the #tbl pin is tied to low state, then boot block is locked no matter how the software is set. like the dq2, the dq3 inversely mirrors the #wp state. if the dq3 is ?0?, it means the #wp pin is in high state, then all the sectors ex cept the boot block can be programmed/erased. on the other hand, if the dq3 is ?1?, then all the se ctors except the boot block are programmed/erased inhibited. to return to normal operation, perform a three-by te command sequence (or an alternate single-byte command) to exit the identification mode. fo r the specific code, see command codes for identification/boot block lockout detection.
W39V080FA - 6 - 6.6 sector erase command sector erase is a six bus cycles operation. there are two "unlock" write cycles , followed by writing the "set-up" command. two more "unlock" write cycles then follows by the sector erase command. the sector address (any address location within the desir ed sector) is latched on the rising edge of r/#c in programmer mode, while the command (30h) is latched on the rising edge of #we. sector erase does not require the user to program the device prior to erase. when erasing a sector, the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the erase co mmand is completed, right from the rising edge of the #we pulse for the last sector erase command pulse and terminates when the data on dq7, data polling, is "1" at which time the device returns to the read mode. data polling must be performed at an address within any of t he sectors being erased. refer to the erase command flow chart using typical command strings and bus operations. 6.7 program operation the W39V080FA is programmed on a byte-by-byte basis. program operation can only change logical data "1" to logical data "0." the erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. the program operation is initiated by a 4-byte command cycle (see command codes for byte programming). the device will internally enter the program operation immediately after the byte-program command is entered. the internal program timer will automatically time-out (9 s typ.-t bp ) once it is completed and then return to normal read mode. data polling and/or toggle bits can be used to detect end of program cycle. 6.8 dual bios the W39V080FA provides a solution for dual-bios app lication. in fwh mode, wh en d/#f is low, the device functions as a full-chip partition of 8m-b it which address ranges from fffffh to 00000h with a[19:0]. if d/#f is driven high, the device function s as a dual-block partition that each block consists of 4m-bit. for dual-block partition, there is only one 4m-bit block, either upper or lower, can be accessed. the u/#l pin selects either upper or lower 4m-bit block and its address ranges from 7ffffh to 00000h with a[19:0]. when u/#l is low, the lower 4m-bit block will be selected; while, u/#l is high, the upper 4m-bit block will be selected. 6.9 hardware data protection the integrity of the data stored in the W39V080FA is also hardware protected in the following ways: (1) noise/glitch protection: a #we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming and read operation are inhibited when v dd is less than 2.0v typical. (3) write inhibit mode: forcing #oe low or #we high will inhibit the write operation. this prevents inadvertent writes during powe r-up or power-down periods.
W39V080FA publication release date: dec. 13, 2005 - 7 - revision a5 6.10 write operation status the device provides several bits to determine the st atus of a program or erase operation: dq5, dq6, and dq7. each of dq7 and dq6 provides a method for determining whether a program or erase operation is complete or in progress. the device also offers a hardware-based output signal, ry/#by in programmer mode, to determine whether an embedded program or erase operat ion is in progress or has been completed. 6.10.1 dq7: #data polling the #data polling bit, dq7, indicates whether an embedd ed program or erase algorithm is in progress or completed. data polling is valid after the rising edge of the final #we pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 and the complement of the data programmed to dq7. once the embedded program al gorithm has completed, the device outputs the data programmed to dq7. the system must prov ide the program address to read valid status information on dq7. if a program address falls within a protected sector, #data polling on dq7 is active for about 1 s, and then the device returns to the read mode. during the embedded erase algorithm, #data polli ng produces ?0? on dq7. once the embedded erase algorithm has completed, #data polling produces ?1? on dq7. an address within any of the sectors selected for erasure mu st be provided to read valid status information on dq7. after an erase command sequence is written, if a ll sectors selected for eras ing are protected, #data polling on dq7 is active for about 100 s, and then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that ar e protected. however, if the syst em reads dq7 at an address within a protected sector, the status may not be valid. just before the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0-dq6 while output enable (#oe) is set to low. that is, the device may change from providing status information to va lid data on dq7. depending on when it samples the dq7 output, the system may read the status or valid dat a. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0-dq6 may be still invalid. valid data on dq7-dq0 will appear on successive read cycles. 6.10.2 ry/#by: ready/#busy the ry/#by is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/#by status is valid after the rising edge of the final #we pulse in the command sequence. since ry/#by is an open-drain output, several ry/#by pins can be tied together in parallel with a pull-up resistor to v dd . when the output is low (busy), the device is acti vely erasing or programming. when the output is high (ready), the device is in t he read mode or standby mode. 6.10.3 dq6: toggle bit toggle bit on dq6 indicates whether an embedded program or erase algorithm is in progress or complete. toggle bit i may be read at any address, and is valid after the rising edge of the final #we pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operat ion, successive read cycles to any address cause dq6 to toggle. the system may use either #o e to control the read cycles. once the operation has completed, dq6 stops toggling.
W39V080FA - 8 - after an erase command sequence is written, if a ll sectors selected for erasing are protected, dq6 toggles for about 100 s, and then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases th e unprotected sectors, and ignores the selected sectors which are protected. the system can use dq6 to determine whether a sector is actively erasing. if the device is actively erasing (i.e., the embedded erase algorithm is in progress), dq6 toggles. if a program address falls within a protected sector, dq6 toggles for about 1 s after the program command sequence is written, and then returns to reading array data. 6.10.4 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. dq5 produces ?1? under these conditions which indi cates that the program or erase cycle was not successfully completed. the device may output ?1? on dq5 if the system tries to program ?1? to a location that was previously programmed to ?0.? only the erase operation can change ?0? back to ?1.? under this condition, the device stops the operation, and while the timi ng limit has been exceeded, dq5 produces ?1.? under both these conditions, the system must hardware reset to return to the read mode. 6.11 identification input pin id[3:0] these pins are part of mechanism that allows multiple parts to be used on the same bus. the boot device should be 0000b. and all the subsequent parts should use the up-count strapping. 6.12 register there are three kinds of re gisters on this device, the general pu rpose input registers, the block lock control registers and product ident ification registers. users can access these registers through respective address in the 4gbytes memory map. th ere are detail descriptions in the sections below. 6.12.1 general purpose inputs register this register reads the fgpi[4:0] pins on the w39v 080fa.this is a pass-through register which can read via memory address ffbc0100(hex). since it is pass-through register, there is no default value. gpi register table bit function 7 ? 5 reserved 4 read fgpi4 pin status 3 read fgpi3 pin status 2 read fgpi2 pin status 1 read fgpi1 pin status 0 read fgpi0 pin status 6.12.2 block locking registers this part provides 16 even 64kby tes blocks, and each block can be lo cked by register control. these control registers can be set or clear through me mory address. below is the detail description.
W39V080FA publication release date: dec. 13, 2005 - 9 - revision a5 block locking registers type and access memory map table registers registers type control block device physical address 4gbytes system memory address blr15 r/w 15 0fffffh ? 0f0000h ffbf0002h blr14 r/w 14 0effffh ? 0e0000h ffbe0002h blr13 r/w 13 0dffffh ? 0d0000h ffbd0002h blr12 r/w 12 0cffffh ? 0c0000h ffbc0002h blr11 r/w 11 0bffffh ? 0b0000h ffbb0002h blr10 r/w 10 0affffh ? 0a0000h ffba0002h blr9 r/w 9 09ffffh ? 090000h ffb90002h blr8 r/w 8 08ffffh ? 080000h ffb80002h blr7 r/w 7 07ffffh ? 070000h ffb70002h blr6 r/w 6 06ffffh ? 060000h ffb60002h blr5 r/w 5 05ffffh ? 050000h ffb50002h blr4 r/w 4 04ffffh ? 040000h ffb40002h blr3 r/w 3 03ffffh ? 030000h ffb30002h blr2 r/w 2 02ffffh ? 020000h ffb20002h blr1 r/w 1 01ffffh ? 010000h ffb10002h blr0 r/w 0 00ffffh ? 000000h ffb00002h block locking register bits function table bit function 7 ? 3 reserved 2 read lock 1: prohibit to read in the block where set 0: normal read operation in the block where clear. this is default state. 1 lock down 1: prohibit further to set or clear the read lock or write lock bits. this lock down bit can only be set not clear. only the device is reset or re-powered, the lock down bit is cleared. 0: normal operation for read lock or wr ite lock. this is the default state. 0 write lock 1: prohibited to write in the block where set. this is default state. 0: normal programming/erase operat ion in the block where clear.
W39V080FA - 10 - register based block locking value definitions table bit [7:3] bit 2 bit 1 bit 0 result 00000 0 0 0 full access. 00000 0 0 1 write lock. default state. 00000 0 1 0 locked open (full access, lock down). 00000 0 1 1 write locked, locked down. 00000 1 0 0 read locked. 00000 1 0 1 read & write locked. 00000 1 1 0 read locked, locked down. 00000 1 1 1 read & write locked, locked down. read lock any attempt to read the data of read locked block will result in ?00h.? the default state of any block is unlocked upon power up. user can clear or set the writ e lock bit anytime as long as the lock down bit is not set. write lock this is the default state of blocks upon power up. be fore any program or erase to the specified block, user should clear the write lock bit first. user can cl ear or set the write lock bit anytime as long as the lock down bit is not set. the write lock function is in conjunction with the hardware protect pins, #wp & tbl. when hardware protect pins are enabled, it w ill override the register block locking functions and write lock the blocks no matter how the status of the register bits. reading the register bit will not reflect the status of the #wp or #tbl pins. lock down the default state of lock down bit for any block is unlocked. this bit can be set only once; any further attempt to set or clear is ignored. only the reset from #reset or #init can clear the lock down bit. once the lock down bit is set for a block, then the wr ite lock bit & read lock bit of that block will not be set or cleared, and keep its current state. 6.12.3 product identification registers there is an alternative software method to read out the product identification in both the programmer interface mode and the fwh interface mode. thus , the programming equipment can automatically matches the device with its proper erase and programming algorithms. in the full-chip(8mb) fwh interface mode, a read fr om ffbc, 0000(hex) can output the manufacturer code, da(hex). a read from ffbc, 0001(hex ) can output the device code, d3(hex). for dual-bios(4mbx2) fwh mode , a read from ffbc, 0000(hex) can output the manufacturer code, da(hex). a read from ffbc,0001(hex) can output the device code 93(hex). in the software access mode, a jedec 3-byte comm and sequence can be used to access the product id for programmer interface mode. a read from address 0000(hex) outputs the manufacturer code, da(hex). a read from address 0001( hex) outputs the device code, d3( hex).? the product id operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see command definition table for detail).
W39V080FA publication release date: dec. 13, 2005 - 11 - revision a5 6.13 table of operating modes 6.13.1 operating mode selection - programmer mode mode pins #oe #we #reset address dq. read v il v ih v ih ain dout write v ih v il v ih ain din standby x x v il x high z write inhibit v il x v ih x high z/dout x v ih v ih x high z/dout output disable v ih x v ih x high z 6.13.2 operating mode selection - fwh mode operation modes in fwh interface mode are determin ed by "start cycle" when it is selected. when it is not selected, its output s (fwh[3:0]) will be disable. pl ease reference to the "fwh cycle definition". table of command definition command no. of 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle description cycles (1) addr. data addr. data addr. data addr. data addr. data addr. data read 1 a in d out sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (5) 30 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (4) 3 5555 aa 2aaa 55 5555 f0 product id exit (4) 1 xxxx f0 notes: 1. the cycle means the write command cycle not the fwh clock cycle. 2. the column address / row address are mapped to the low / high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[19:11] 3. address format: a14 ? a0 (hex); data format: dq7-dq0 (hex) 4. either one of the two product id exit commands can be used. 5. sa: sector address sa = fxxxxh for unique sector15 (boot se ctor) sa = 7xxxxh for unique sector7 sa = exxxxh for unique sector14 sa = 6xxxxh for unique sector6 sa = dxxxxh for unique sector13 sa = 5xxxxh for unique sector5 sa = cxxxxh for unique sector12 sa = 4xxxxh for unique sector4 sa = bxxxxh for unique sector11 sa = 3xxxxh for unique sector3 sa = axxxxh for unique sector10 sa = 2xxxxh for unique sector2 sa = 9xxxxh for unique sector9 sa = 1xxxxh for unique sector1 sa = 8xxxxh for unique sector8 sa = 0xxxxh for unique sector0
W39V080FA - 12 - 6.14 fwh cycle definition field no. of clocks description start 1 "1101b" indicates fwh memory read cycle; while "1110b" indicates fwh memory write cycle. 0000b" appears on fwh bus to indicate the initial idsel 1 this one clock field indicates which fwh component is being selected. msize 1 memory size. there is always show ?0000b? for single byte access. tar 2 turned around time addr 7 address phase for memory cycle. fwh supports the 28 bits address protocol. the addresses transfer most significant nibble first and least significant nibble last. (i.e. address[27:24] on fwh[3:0] first, and address[3:0] on fwh[3:0] last.) sync n synchronous to add wait state. "0000b" means ready, "0101b" means short wait, "0110b" means long wait, "1001b" for dma only, "1010b" means error, and other values are reserved. data 2 data phase for memory cycle. the data transfer least significant nibble first and most significant nibble last. (i.e. dq[3:0] on fwh[3:0] first, then dq[7:4] on fwh[3:0] last.)
W39V080FA publication release date: dec. 13, 2005 - 13 - revision a5 6.15 embedded programming algorithm start write program command sequence (see below) programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit program command sequence (address/command):
W39V080FA - 14 - 6.16 embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h sector address/30h (address/command): individual sector erase command sequence
W39V080FA publication release date: dec. 13, 2005 - 15 - revision a5 6.17 embedded #data polling algorithm start read byte (dq0 - dq7) address = sa pass dq7 = data ? yes fail dq5 = 1 no read byte (dq0 - dq7) address = sa dq7 = data yes no yes no note: sa = valid address for programming .during a sector erase operation, a valid address is an address within any sector selected for erasure.
W39V080FA - 16 - 6.18 embedded toggle bit algorithm yes no pass read byte (dq0-dq7) start read byte (dq0-dq7) dq5 = 1 ? read byte (dq0-dq7) twin toggle bit =toggle ? toggle bit =toggle ? fail no yes no note: recheck toggle bit because it may stop toggling as dq5 changes to ?1? .
W39V080FA publication release date: dec. 13, 2005 - 17 - revision a5 6.19 software product identification and boot block lockout detection acquisition flow product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 00000 data = da read address = 00001 data = d3 read address = ffff2 check dq[3:0] of data outputs (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 load data aa to address 5555 pause 10 s notes for software product identificat ion/boot block lockout detection: (1) data format: dq7 ? dq0 (hex); address format: a14 ? a0 (hex) (2) a1 ? a19 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block lockout detection mode if power down. (4) the dq[3:2] to indicate the sectors protect status as below: dq2 dq3 0 64kbytes boot block unlocked by #tbl hardware trapping whole chip unlocked by #wp hardware trapping except boot block 1 64kbytes boot block locked by #tbl hardware trapping whole chip locked by #wp hardware trapping except boot block (5) the device returns to standard operation mode. (6) optional 1-write cycle (write f0 (hex .) at xxxx address) can be used to exit the product identification/boot block lockout detection.
W39V080FA - 18 - 7. dc characteristics 7.1 absolute maximum ratings parameter rating unit power supply voltage to v ss potential -0.5 to +4.0 v operating temperature 0 to +70 c storage temperature -65 to +150 c d.c. voltage on any pin to ground potential -0.5 to v dd +0.5 v v pp voltage -0.5 to +13 v transient voltage (<20 ns) on any pin to ground potential -1.0 to v dd +0.5 v note : exposure to conditions beyond those lis ted under absolute maximum ratings may adversely affect the life and reliability of the device. 7.2 programmer interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current (read) i cc1 in read or write mode, all dqs open address inputs = 3.0v/0v, at f = 3 mhz - 15 20 ma power supply current (erase/ write) i cc2 in read or write mode, all dqs open address inputs = 3.0v/0v, at f = 3 mhz - 35 45 ma input leakage current i li v in = v ss to v dd - - 90 a output leakage current i lo v out = v ss to v dd - - 90 a input low voltage v il - -0.5 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = -0.1ma 2.4 - - v
W39V080FA publication release date: dec. 13, 2005 - 19 - revision a5 7.3 fwh interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current (read) i cc1 all i out = 0a, clk = 33 mhz, in fwh mode operation. - 15 20 ma power supply current (erase/write) i cc2 all i out = 0a, clk = 33 mhz, in fwh mode operation. - 35 45 ma standby current 1 isb1 fwh4 = 0.9 v dd , clk = 33 mhz, all inputs = 0.9 v dd / 0.1 v dd no internal operation - 20 50 ua standby current 2 isb2 fwh4 = 0.1 v dd , clk = 33 mhz, all inputs = 0.9 v dd /0.1 v dd no internal operation. - 3 10 ma input low voltage v il - -0.5 - 0.3 v dd v input low voltage of #init v ili - -0.5 - 0.2 v dd v input high voltage v ih - 0.5 v dd - v dd +0.5 v input high voltage of #init pin v ihi - 1.35 v - v dd +0.5 v output low voltage v ol i ol = 1.5 ma - - 0.1 v dd v output high voltage v oh i oh = -0.5 ma 0.9 v dd - - v 7.4 power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 s power-up to write operation t pu . write 5 ms 7.5 capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf
W39V080FA - 20 - 8. programmer interface mode ac characteristics 8.1 ac test conditions parameter conditions input pulse levels 0v to 0.9 v dd input rise/fall time < 5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf 8.2 ac test load and waveform +3.3v 1.8k 1.3k d out 30 pf (including jig and scope) input 0.9vdd 0v test point test point 1.5v 1.5v output
W39V080FA publication release date: dec. 13, 2005 - 21 - revision a5 programmer interface mode ac characteristics, continued 8.3 read cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) W39V080FA parameter symbol min. max. unit read cycle time t rc 350 - ns row / column address set up time t as 50 - ns row / column address hold time t ah 50 - ns address access time t aa - 200 ns output enable access time t oe - 75 ns #oe low to active output t olz 0 - ns #oe high to high-z output t ohz - 35 ns output hold from address change t oh 0 - ns 8.4 write cycle timing parameters parameter symbol min. typ. max. unit reset time t rst 1 - - s address setup time t as 50 - - ns address hold time t ah 50 - - ns r/#c to write enable high time t cwh 50 - - ns #we pulse width t wp 100 - - ns #we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 50 - - ns #oe hold time t oeh 0 - - ns byte programming time t bp - 9 250 s sector erase cycle time (note (c)) t pec - 0.9 6 s program/erase valid to ry/#by delay t busy 90 - - ns note: all ac timing signals observe the following guideli nes for determining setup and hold times: (a) high level signal's refe rence level is input high and (b) low level signal's reference level is i nput low. ref. to the ac testing condition. (c) exclude 00h pre-program prior to erasure. (in the pre- programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure 8.5 data polling and toggle bit timing parameters W39V080FA parameter symbol min. max. unit #oe to data polling output delay t oep - 40 ns #oe to toggle bit output delay t oet - 40 ns toggle or polling interval --- 50 - ms
W39V080FA - 22 - 9. timing waveforms for programmer interface mode 9.1 read cycle timing diagram dq[7:0] high-z #oe #we v ih t oh t aa data valid t ohz high-z t olz t oe #reset a[10:0] t rc r/#c t as t ah row address column address t as t ah column address row address t rst 9.2 write cycle timing diagram data valid t cwh t oeh t wp t ds t as t ah t wph t dh dq[7:0] #oe #we #c r/ #reset a[10:0] column address row address t rst t as t ah
W39V080FA publication release date: dec. 13, 2005 - 23 - revision a5 timing waveforms for programmer interface mode, continued 9.3 program cycle timing diagram a[10:0] byte 0 byte 1 byte 2 internal write start dq[7:0] #oe #we byte program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 programmed address data-in byte 3 note: the internal address a[19:0] are converted from external column/row address. column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[8:0] are mapped to the internal a[19:11]. #c r/ (internal a[19:0]) t busy ry/#by 9.4 #data polling timing diagram a[10:0] dq7 #we #oe x x x t oep t bp #c r/ x (internal a[19:0]) an an an an ry/#by t busy
W39V080FA - 24 - timing waveforms for programmer interface mode, continued 9.5 toggle bit timing diagram a[10:0] dq6 #we #oe t oet t bp #c r/ ry/#by 9.6 sector erase timing diagram (internal a[19:0]) sb2 sb1 sb0 a[10:0] dq[7:0] #oe #we sb3 sb4 sb5 internal erase starts six-byte code for 3.3v-only sector erase t wp t wph t pec 5555 2aaa 5555 5555 2aaa sa aa 55 80 aa 55 30 sa = sector address, please ref. to the "table of command definition" note: the internal address a[19:0] are converted from external column/row address. column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[8:0] are mapped to the internal a[19:11]. #c r/ t busy ry/#by
W39V080FA publication release date: dec. 13, 2005 - 25 - revision a5 10. fwh interface mode ac characteristics 10.1 ac test conditions parameter conditions input pulse levels 0.6 v dd to 0.2 v dd input rise/fall slew rate 1 v/ns input/output timing level 0.4v dd / 0.4v dd output load 1 ttl gate and c l = 10 pf 10.2 read/write cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) W39V080FA parameter symbol min. max. unit clock cycle time t cyc 30 - ns input set up time t su 7 - ns input hold time t hd 0 - ns clock to data valid t kq 2 11 ns note: minimum and maximum time have different load. please refer to pci specification. 10.3 reset timing parameters parameter symbol min. typ. max. unit vdd stable to reset active t prst 1 - - ms clock stable to reset active t krst 100 - - s reset pulse width t rstp 100 - - ns reset active to output float t rstf - - 50 ns reset inactive to input active t rst 10 - - s note: all ac timing signals observe the following guidelines for determining setup and hold times: (a) high level signal's refere nce level is input high and (b) low level signal's reference level is input low. please refer to the ac testing condition.
W39V080FA - 26 - 11. timing waveforms for fwh interface mode 11.1 read cycle timing diagram t cyc fwh4 #reset fwh[3:0] start fwh read idsel clk 1 clock 2 clocks a[15:12] address sync tar 1111b tri-state 0000b t kq t hd t su a[11:8] a[7:4] 0000 b] data out 2 clocks d[7:4] data d[3:0] next start 1 clock 0000b t hd t su load address in 7 clocks a[3:0] m size xxxxb xa[22]xxb a[19:16] 1 clock 1 clock 0000b 1101b note: when a22 = high, the host will read the bios code from the fwh device. while a22 = low, the host will read the gpi (add = ffbc0100) or product id (add = ffbc0000/ffbc0001) from the fwh device 1111b tri-state 2 clocks tar 11.2 write cycle timing diagram t cyc fwh4 #reset fwh[3:0] start fwh write idsel clk next start 1 clock 1 clock a[15:12] load data in 2 clocks d[7:4] address sync 2 clocks tar data 1111b tri-state 0000b t hd t su a[11:8] a[7:4] 0000b d[3:0] 0000b load address in 7 clocks a[3:0] m size xxxxb xxxxb 1 clock 1 clock 0000b 1110b 2 clocks tar 1111b tri-state a[19:16]
W39V080FA publication release date: dec. 13, 2005 - 27 - revision a5 timing waveforms, for fwh interface mode, continued 11.3 program cycle timing diagram fwh4 #reset fwh[3:0 ] 1st start idsel load address "5555" in 7 clocks clk 1 clock 2 clocks load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in fwh mode. 2nd start load address "2aaa" in 7 clocks 1 clock 2 clocks load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in fwh mode. fwh4 #reset fwh[3:0 ] clk #reset clk address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b idsel 0000b 0000b x101b 0101b 0101b 0101b x010b 1010b 1010b 1010b m size m size xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b start next command 1 clock 2 clocks tar 1111b tri-state start next command 1 clock 2 clocks tar 1111b tri-state 3rd start load address "5555" in 7 clocks 1 clock 2 clocks load data "a0" in 2 clocks 1010b 0000b write the 3rd command to the device in fwh mode. 4th start load ain in 7 clocks fwh4 fwh[3:0 ] fwh4 #reset fwh[3:0 ] clk sync internal program start tar 1 clock 2 clocks a[15:12] load din in 2 clocks d[7:4] write the 4th command ( tar g et location to be p ro g rammed ) to the device in fwh mode. a[11:8] a[7:4] a[3:0] d[3:0] 1111b tri-state 0000b data address address sync tar data 1111b tri-state 0000b internal program start idsel idsel 0000b 0000b x101b 0101b 0101b 0101b m size m size xxxxb xxxxb xxxxb a[19:16] xxxxb xxxxb 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b start next command 1 clock 2 clocks tar 1111b tri-state tar 2 clocks 1111b tri-state
W39V080FA - 28 - timing waveforms for fwh interface mode, continued 11.4 #data polling timing diagram read the dq7 to see if the internal write complete or not. fwh4 #reset fwh[3:0] start load address in 7 clocks clk 1 clock 2 clocks xxxxb an[15:12] address sync tar 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] data out 2 clocks dn7,xxx data xxxxb fwh4 #reset fwh[3:0] start load address in 7 clocks clk 1 clock 2 clocks address sync tar 1111b tri-state 0000b data out 2 clocks data when internal write complete, the dq7 will equal to dn7. dn7,xxx xxxxb an[15:12] an[11:8] an[7:4] an[3:0] fwh4 #reset fwh[3:0] start load address "an" in 7 clocks clk 1 clock 2 clocks an[15:12] load data "dn" in 2 clocks dn[7:4] write the last command(program or erase) to the device in fwh mode. address sync tar data 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] dn[3:0] idsel idsel idsel 0000b 0000b 0000b m size m size m size xxxxb an[a19:16] xxxxb xxxxb an[19:16] xxxxb xxxxb an[19:16] xxxxb 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start 1 clock 1 clock 0000b 1101b 1 clock 1 clock 0000b 1101b 1 clock 1 clock 0000b 1110b
W39V080FA publication release date: dec. 13, 2005 - 29 - revision a5 timing waveforms for fwh interface mode, continued 11.5 toggle bit timing diagram read the dq6 to see if the internal write complete or not. fwh4 #reset start load address in 7 clocks clk 1 clock 2 clocks address sync tar 1111b tri-state 0000b data out 2 clocks x,d6,xxb data xxxxb fwh4 #reset fwh[3:0] start load address in 7 clocks clk 1 clock 2 clocks address sync tar 1111b tri-state 0000b data out 2 clocks data when internal write complete, the dq6 will stop toggle. x,d6,xxb xxxxb fwh4 #reset fwh[3:0] start load address "an" in 7 clocks clk 1 clock 2 clocks a[15:12] load data "dn" in 2 clocks d[7:4] write the last command(program or erase) to the device in fwh mode. address sync tar data 1111b tri-state 0000b a[11:8] a[7:4] a[3:0] d[3:0] idsel xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb idsel idsel 0000b 0000b 0000b m size m size m size xxxxb xxxxb xxxxb xxxxb xxxxb a[19:16] xxxxb xxxxb xxxxb 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1101b 1 clock 1 clock 0000b 1101b 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start fwh[3:0]
W39V080FA - 30 - timing waveforms for fwh interface mode, continued 11.6 sector erase timing diagram 6th start load sector address in 7 clocks sync internal erase start 1 clock load din in 2 clocks 0011b write the 6th command ( tar g et sector to be erased ) to the device in fwh mode . 0000b tar 2 clocks 1111b tri-state 0000b data address #reset 1st start load address "5555" in 7 clocks clk 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in fwh mode. fwh4 #reset fwh[3:0] clk fwh4 #reset fwh[3:0] clk fwh4 #reset clk address sync tar data 2nd start load address "2aaa" in 7 clocks 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in fwh mode. 3rd start load address "5555" in 7 clocks 1 clocks 1 clocks start next command 1 clocks 2 clocks 1 clocks x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in fwh mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b 4th start load address "5555" in 7 clocks 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in fwh mode. 5th start load address "2aaa" in 7 clocks 1 clock 1 clock start next command 1 clock 1 clock x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in fwh mode. address address sync 2 clocks tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b fwh4 #reset fwh[3:0] clk fwh4 #reset fwh[3:0] clk xxxxb xxxxb xxxxb idsel internal erase start 0000b 1110b idsel 0000b 1110b idsel 0000b 1110b idsel 0000b 1110b idsel 0000b 1110b idsel 0000b 0000b 0000b 0000b 0000b 0000b m size m size m size m size m size m size xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb a[19:16] xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb tar 2 clocks 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 1 clock 1 clock 0000b 1110b fwh[3:0] fwh4 fwh[3:0] xxxxb
W39V080FA publication release date: dec. 13, 2005 - 31 - revision a5 timing waveforms for fwh interface mode, continued 11.7 fgpi register/product id readout timing diagram note: during the gpi read out mode, the dq[4:0] will capture the states(high or low) of the fgpi[4:0] input pins. the dq[7:5] a re reserved pin s #reset fwh[3:0] start idsel load address "ffbc0100(hex)" in 7 clocks for gpi register & "ffbc0000(hex)/ffbc0001(hex) for product id clk 1 clock 1 clock next st a 1 clock 2 clocks 1 cloc k 0000b 1101b address sync tar 1111b tri-state 0000b data out 2 clocks d[7:4] data 0000b 0001b /0000b 0000b 0000b /0001b d[3:0] a[27:24] a[23:20] a[19:16] 0000b m size 2 clocks tar 1111b tri-state fwh4 11.8 reset timing diagram clk vdd #reset fwh[3:0] t prst t krst t rstp t rstf t rst fwh4
W39V080FA - 32 - 12. ordering information part no. access time (ns) fwh mode power supply current typ. (ma) fwh mode standby vdd current typ. (ua ) package W39V080FAp 11 15 20 32l plcc W39V080FAq 11 15 20 32l stsop W39V080FAt 11 15 20 40l tsop W39V080FApz 11 15 20 32l plcc lead free W39V080FAqz 11 15 20 32l stsop lead free W39V080FAtz 11 15 20 40l tsop lead free notes: 1. winbond reserves the right to make c hanges to its products without prior notice. 2. purchasers are responsible for per forming appropriate quality assurance te sting on products intended for use in applications where personal injury might occur as a consequence of product failure. 13. how to read the top marking example: the top marking of 32-pin stsop W39V080FAqz 1 st line: winbond logo 2 nd line: the part number: W39V080FAqz 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: packages made in ?01, week 49 o: assembly house id : a means ase, o means ose, ...etc. b: ic revision; a means version a, b means version b, ...etc. sa: process code z: lead free W39V080FAqz 2138977a-a12 149obsa
W39V080FA publication release date: dec. 13, 2005 - 33 - revision a5 14. package dimensions 14.1 32l plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusio 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 14.2 32l stsop (8x14mm) min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm a a a 2 1 l l 1 y e h d d c b e
W39V080FA - 34 - package dimensions, continued 14.3 40l tsop (10 mm x 20 mm)
W39V080FA publication release date: dec. 13, 2005 - 35 - revision a5 15. version history version date page description a1 nov. 25, 2004 - initial issued a2 jan. 05, 2005 8 add 6.11 identification input pin id[3:0] item add 6.12.3 product ident ification registers dual bios device id 93(hex) a3 april 14, 2005 35 add important notice a4 oct. 3, 2005 3 revise endurance 10k cycles to 30k cycles a5 dec. 13, 2005 8, 16 revise 6.10.4 dq5: exceeded timing limits description, and page16 embedded toggle bit algorithm important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical im plantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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